module mux_4to1 (
    out, in0, in1, in2, in3, addr
);

    parameter counter_bits = 4;
    output reg [counter_bits-1:0] out;
    input [counter_bits-1:0] in0, in1, in2, in3;
    input[1:0] addr;

    always @(*) begin
        case ( addr )
            0 : out = in0;
            1 : out = in1;
            2 : out = in2;
            3 : out = in3;
            default : out = 0;
        endcase
    end

endmodule